973b27b91d
One problem with the cpuid instruction is that it uses %ebx which, when code is compiled as PIC for i386, is used as the PIC base register. This patch tries to handle this case by replacing the second register (%1) constraint with "=r", i.e. any (other) register, and swapping %ebx and %1 around the cpuid instruction. This patch could use a test, preferably on real i686 hardware. At least it needs some review and perhaps inspection of the generated assembler output. The idea and reasoning was taken from this comment: http://gcc.gnu.org/ml/gcc-patches/2007-09/msg00324.html
34 lines
926 B
Diff
34 lines
926 B
Diff
--- utils/cpuid.h 2010-07-05 17:43:17.000000000 +0200
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+++ utils/cpuid.h 2016-10-13 22:31:26.988374329 +0200
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@@ -1,6 +1,21 @@
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#ifndef _CPUFREQ_CPUID_H
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#define _CPUFREQ_CPUID_H
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+#if defined(__i386__) && defined(__PIC__)
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+static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
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+ unsigned int *ecx, unsigned int *edx)
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+{
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+ /* ecx is often an input as well as an output. */
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+ asm volatile("xchgl\t%%ebx, %1\n\t" \
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+ "cpuid\n\t" \
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+ "xchgl\t%%ebx, %1"
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+ : "=a" (*eax),
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+ "=r" (*ebx),
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+ "=c" (*ecx),
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+ "=d" (*edx)
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+ : "0" (*eax), "2" (*ecx));
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+}
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+#else
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static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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@@ -12,6 +27,8 @@
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx));
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}
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+#endif
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+
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static inline void cpuid(unsigned int op,
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unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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